A new system for BIST architecture generation for embedded memories in SoCs

The paper is aimed at a new system for generation of suitable BIST (Built-in Self-Test) blocks for effective testing of multiple memories integrated in a SoC (System on Chip). Incoming technologies, chip complexity and increasing clock frequencies give new challenges for testing huge number of embedded SoC memories. SoCs have to be tested after their manufacturing and always during their life-time. The reliability of nowadays SoCs and their life-time depend mainly on the reliability of embedded memories, which can occupy more than 70 % of the chip area [1]. Thus memories have to be tested carefully for different types of faults. Memory BIST technique is one of the efficient approaches for testing memories and for keeping test quality and its frequency at desirable levels. The quality of fault coverage basically depends on applied test algorithms related to targeted faults. The problem is how to test more than hundred or thousand of memories integrated inside SoCs by BIST. Using one BIST to test all memories serially is a time consuming process. On the other hand, adding a test wrapper to each memory would enable parallel testing. Parallel testing is time-effective but some other aspects become problematic such as higher area overhead and high power consumption. Current hybrid BIST techniques use both serial and parallel testing. They utilize a combination of serial and parallel test wrappers for embedded memories and testing is controlled via central control unit (BIST controller). Common SoCs with hundreds of memories on chip already use such BIST techniques and these test techniques have to be continually improved. Thus, embedded memories can be tested in parallel or in serial depending on the test constraints. Test constrains mean the test quality in the context of fault coverage, test length related to testing time, area overhead and power consumption during test application. A hybrid technique seems to be the best BIST method for testing multiple memories with various parameters and designing a suitable BIST architecture for a SoC. The parameters are defined a) from the test constrains, and b) from memories and their position within the SoC. A general scheme of hybrid testing is depicted in fig. 1 containing 8 memory blocks. The BIST controller controls both serial and parallel testing. Its complexity and functionality depend on the Fig. 1. BIST architecture for memories in SoC.